Fully depleted SOI (FDSOI) technology

Reliability Evaluation of Fully Depleted SOI (FDSOI) Technology for Space Applications

Metal Gate Technology for Fully Depleted SOI CMOS

This paper reviews recent approaches in the development of a tunable work function metal gate CMOS technology and describes the application of one such approach to the fabrication of metal gate fullydepleted (FD) SOI transistor structures such as the ultra-thin body (UTB) FET and the FinFET.

Fully Depleted SOI MOSFETs for DRAM

SOI technology has received high attention for the future high density DRAM applications. The two major requirements in any DRAM technology are long retention time and high charging efficiency. This paper discusses the disadvantages of using bulk silicon and Partially Depleted SOI devices in these terms. It is shown that a DRAM cell built with fully depleted SOI MOSFETs can store data for a lon...

Low frequency noise in 0.12 mum partially and fully depleted SOI technology

Low frequency noise characterisation of 0.12 μm SOI CMOS technology was performed for Partially and Fully Depleted N-MOSFETs. Static performances are first presented, then we address the drain current fluctuations in both linear and saturation regimes. Taking into consideration the usually admitted 1/f noise models in MOS devices and their applicability in our case, we finally point out the enh...

A Monolithic Pixel Sensor in 0.15 μm Fully Depleted SOI Technology

This letter presents the design of a monolithic pixel sensor with 10×10 μm pixels in OKI 0.15 μm fully depleted SOI technology and first results of its characterisation. The response of the chip to charged particles has been studied on the 1.35 GeV e− beam at the LBNL ALS.